1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly, to a stacked chip package that includes heat transfer wires.
2. Description of the Related Art
The electronic industry continues to seek products that are lighter, faster, smaller, multi-functional, more reliable and more cost-effective. In order to meet the requirement of the electronic industries, circuit chips must become highly integrated.
However, enhancing the density of chips for purposes of making them highly integrated is expensive and has technical limitations. Therefore, three-dimensional semiconductor packaging technologies have been developed and are being used. In general, package stacks made by stacking a plurality of packages, and stacked chip packages made by stacking a plurality of chips, are broadly known.
It is possible to achieve high density of integration by using package stacks. However, the thickness of the individual packages may increase the thickness of the package stacks. Compared with package stacks, it is possible not only to achieve a high density of integration but also to minimize the thickness by using stacked chip packages.
Referring to FIG. 1, the conventional structure of the stacked chip package (100) will be explained. As shown in FIG. 1, two chips (21, 22) are stacked on a substrate (10). The two stacked chips (21, 22) are connected to the substrate (10) electrically by bonding wires (32, 34). Between the lower chip (21) and the upper chip (22), an adhesive layer (40) is formed which adheres the two chips (21, 22) to each other. The chips (21, 22) and the bonding wires (32, 34) are encapsulated by resin (50) such as Epoxy Molding Compound (EMC). On the rear side of the substrate (10), outer terminals (60), such as solder balls or the like, are formed and connected to the chips (21, 22) by bonding wires (32, 34) and through via holes (not shown in the figure) in the substrate (10).
However, there is a thermal dissipation problem in the conventional stacked chip package shown in FIG. 1. The technical problem in connection with heat dissipation is described in FIG. 2. As shown in FIG. 2, the heat generated by the two chips (21, 22) is transferred to the adhesive layer (40) and trapped therein.
If the heat trapped in the adhesive layer (40) cannot be dissipated, it can result in heating of the chips (21, 22), especially heating of the lower chip (21). Therefore, the performance of the stacked chip package (100) will deteriorate, if the technical problem of the heat trapped in the adhesive layer (40) cannot be solved.